The present invention generally relates to semiconductor devices and more particularly to a high-speed compound semiconductor device having a reduced source resistance.
Compound field effect semiconductor devices such as a MESFET or HEMT have a structure in which a gate electrode is provided on a semiconductor substrate that provides a channel layer, and a pair of ohmic electrodes are formed at both lateral sides of the gate electrode as source and drain electrodes. Thereby, the part of the substrate that contacts the source electrode or drain electrode forms a source region or a drain region. In such compound field effect semiconductor devices, it is desired to reduce the resistance of the source region or drain region as much as possible for improving the operational speed of the semiconductor device.
Thus, there has been a proposal to form an ion-implanted region in the substrate in correspondence to the source region or drain region so as to reduce the source resistance or drain resistance of the semiconductor device similarly to the case of a conventional MOS transistor constructed on a Si substrate.
Generally, formation of such an ion-implanted region is achieved by an ion implantation process, wherein an ion implantation process generally includes a thermal annealing process conducted after the step of introducing accelerated ions, as is well known in the art.
In the case of a III-V compound semiconductor device, however, there is a tendency that the group V element such as As or P causes a dissociation during such an annealing process, and thus, it has been necessary to conduct the annealing process in an atmosphere of the foregoing group V element or in a state in which the surface of the compound semiconductor substrate is covered by an insulation film, for avoiding such a dissociation of the group V element.
FIG. 1 shows an example of a conventional annealing process as applied to a GaAs HFET (heterostructure FET).
Referring to FIG. 1, the GaAs HFET is constructed on a semi-insulating GaAs substrate 11 and includes a first compound semiconductor layer 12A of an undoped GaAs or a low-resistance GaAs doped to the p.sup.- -type on the foregoing semi-insulating GaAs substrate 11. Further, a second compound semiconductor layer 12B is formed on the first compound semiconductor layer 12A as a channel layer of the semiconductor device, wherein the second compound semiconductor layer 12B may be formed of undoped or n-type GaAs, InGaAs or InGaAsP. It should be noted that the first compound semiconductor layer 12A functions as a carrier blocking barrier preventing a leakage of carriers from the channel layer 12B to the substrate 11. Such a leakage of carriers tends to occur in extremely miniaturized devices in which a short channel effect appears conspicuously.
On the channel layer 12B, a gate electrode 13 of WSi is provided, and the channel layer 12B as well as a part of the carrier blocking layer 12A underneath the channel layer 12B are subjected to an ion implantation process of an n-type dopant such as Si.sup.+ at both lateral sides of the WSi gate electrode 13 while using the gate electrode 13 as a self-aligned mask. By applying an annealing process to the structure thus obtained, a source region 12C and a drain region 12D both of the n.sup.+ -type are formed in the channel layer 12B at both lateral sizes of the gate electrode 13.
When applying an annealing process in such a structure, it is generally practiced to provide an insulation film 14 of SiO.sub.2, SiN, AlN or SiON on the substrate 11 for preventing the dissociation of the group V element from the III-V compound semiconductor crystal forming the first or second compound semiconductor layers. Thus, the insulation film 14 is provided so as to cover the channel layer 12B as well as the gate electrode 13 thereon.
After the structure of FIG. 1 is formed, the insulation film 14 is removed selectively, and source and drain electrodes (not illustrated) are formed on the source region 12C and the drain region 12D.
In the foregoing process of FIG. 1, the problem of dissociation occurring in the channel layer 12B, which is essential for the operation of the semiconductor device, is successfully eliminated by conducting the annealing process in the state that the insulation film 14 is provided.
On the other hand, the structure of FIG. 1 includes a triple point A in the structure as indicated, wherein it should be noted that the triple point A is a point in which all of the channel layer 12B, the insulation film 14 and the gate electrode 13 make a contact with each other. Because of the difference in the thermal expansion coefficient, the triple point A tends to accumulate a severe thermal stress, while such a thermal stress in the triple point A tends to induce a stress and hence crystal defects inside the channel layer 12B, particularly in the vicinity of the gate electrode 13. Thereby, the operational performance of the semiconductor device is substantially deteriorated.
Further, the conventional device of FIG. 1 suffers from the problem of difficulty in controlling the profile of the impurity element at the time of the annealing process.
Meanwhile, there is proposed a process of forming a low-resistance source region or a low-resistance drain region by growing a conductive compound semiconductor layer on a compound semiconductor substrate selectively as source and drain regions.
FIGS. 2A-2C show a conventional process of forming a compound field effect semiconductor device 21 carrying the selectively grown source and drain regions.
Referring to FIG. 2A, the semiconductor device is constructed on a semi-insulating GaAs substrate 22 and a channel region 22A of the n-type is formed on the semi-insulating GaAs substrate 22. Further, an insulation layer 23 of SiON is formed on the substrate 22, and the insulation layer 23 is formed with openings 23A and 23B exposing the surface of the substrate 22 in correspondence to the source region and the drain region of the semiconductor device to be formed.
Next, in the step of FIG. 2B, an MOVPE process is conducted by using TMGa (trimethylgallium) or TEGa (triethylgallium) and arsine (AsH.sub.3) respectively as a gaseous source of Ga and As, with silane (SiH.sub.4) added thereto as a gaseous source of dopant. As a result of the MOVPE process, a source region 24A and a drain region 24B of n.sup.+ -type GaAs are grown selectively on the substrate 22 in correspondence to the foregoing openings 23A and 23B. Further, a Schottky electrode 25 is formed in the step of FIG. 2C between the source region 4A and the drain region 4B.
FIG. 3 shows the construction of a MOVPE apparatus 30 used in the step of FIGS. 2A-2C, particularly in the step of FIG. 2B, for forming the source region 24A and the drain region 24B by the selective growth process.
Referring to FIG. 3, the MOVPE apparatus 30 includes a reaction chamber 31 in which a holder 31B is provided in a rotatable manner by a motor 31A, wherein the holder 31B carries a susceptor 31C and the susceptor 31C supports thereon a wafer 31D. Further, a heater 31E is provided in the reaction chamber 31 in correspondence to each of the susceptors 31C.
It should be noted that the MOVPE apparatus 30 further includes a carrier gas line 32 to which a carrier gas such as H.sub.2 is supplied. Further, the MOVPE apparatus 30 includes gas cylinders 33A and 33B respectively holding an arsine gas and a silane gas as an As source and a dopant, wherein arsine in the cylinder 33A is supplied to the reaction chamber 31 via a valve 33a and a line 34, together with the carrier gas supplied to the foregoing line 32. Similarly, silane in the cylinder 33B is supplied to the reaction chamber 31 together with the carrier gas through the line 32, via a valve 33b and the line 34 cooperating with the gas cylinder 33B.
In addition, the MOVPE apparatus 30 of FIG. 3 includes a bubbler 35A holding a Ga source and a bubbler 35B holding a source of another group III element such as In, wherein each of the bubblers 35A and 35B is supplied with a carrier gas from the line 32 for bubbling. As a result of the bubbling, a gaseous source of Ga is formed in the bubbler 35A and the Ga gaseous source thus formed is supplied to the reaction chamber 31 via a valve 35a and the line 34, together with a gaseous source of the other group III element, which is supplied via a valve 35b and the line 34. Further, the cylinders 33A and 33B are provided with valves 33a' and 33b' for purging. Similarly, the bubblers 35A and 35B are provided with valves 35a' and 35b' for purging, wherein the valves 33a' and 33b' and the valves 35a' and 35b' are connected to a purge line 34' which in turn is connected to an external scrubber (not shown). Further, the reaction chamber 33 itself is evacuated via an exhaust line 36 connected to the scrubber.
When TMGa, a substance commonly used in the art of MOVPE as the source of Ga, is used in such a selective growth process conducted by the system of FIG. 3, there arises a problem in that precipitates 24X are formed on the surface of the insulation film 23 during the process of FIG. 2B for forming the source region 24A and the drain region 24B, wherein such precipitates 24X cause an adversary effect on the device characteristic or yield of the MESFET production. While the composition of the precipitates 24X is not analyzed, it is believed that the precipitate 24X is an organic compound containing Ga and As.
It is known that the problem of formation of such precipitates 24X can be avoided by using DEGaCl (diethylgallium chloride) for the source of Ga. However, DEGaCl has a vapor pressure of only 0.1 Torr or less at the room temperature and cannot provide a sufficient deposition rate necessary for production of the device, particularly when used in the deposition system of FIG. 3 in which the reaction chamber 11 has a large volume for mass production according to a batch process.
It is of course possible to increase the deposition rate even when DEGaCl is used, by increasing the evaporation temperature of the bubbler 35A to 50-60.degree. C. However, such a process is not desirable in view of possible thermal interference caused to the adjacent bubblers such as the bubbler 35B. For example, the heat of the bubbler 35A may be transmitted to the bubbler 35B via gas lines and cause an increase in the temperature of the source material held in the bubbler 35B. It should be noted that the control of the bubbling temperature in the bubblers has to be made exactly, typically within a tolerance of .+-.1.degree. C.